1. Field of the Invention
The present invention relates to semiconductor devices. More particularly, the present invention relates to a semiconductor device which detects a potential of an input terminal for a prescribed period and performs operation in accordance with the detected result.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as a DRAM) has a special operating modes such as a mode for reducing test time, as well as normal operating modes including read, write, and refresh modes. Special operating modes include (1) a mode in which a substrate potential can be applied from an external terminal, (2) a mode in which more word lines are selected than normally, and (3) a mode for a device having many I/O lines in which I/O lines are short-circuited internally and the device is tested as a device which seemingly has a small number of I/O lines.
These special operation modes are set by applying to a prescribed input/output terminal a voltage Vh of a super Vcc level higher than a power supply level Vcc by several volts. For this reason, a conventional DRAM is provided with a super Vcc detection circuit for detecting application of voltage Vh of the super Vcc level to a prescribed input/output terminal (see FIG. 1).
FIG. 5 is a circuit diagram showing a structure of a conventional super Vcc detection circuit 50. Referring to FIG. 5, super Vcc detection circuit 50 includes n channel MOS transistors 51-55 and an inverter 56. The n channel MOS transistors 51-54 and inverter 56 are serially connected between, for example, an output enable signal input terminal 15 and an output node N56 of circuit 50. The n channel MOS transistors 51-54 have their gates connected to their drains respectively. The n channel MOS transistor 55 has a drain connected to a connection node N55 between n channel MOS transistor 54 and inverter 56, a source connected to a ground terminal 17, and a gate connected to a power supply terminal 18.
Next, operations of super Vcc detection circuit 50 will be described. For simplicity of description, it is assumed that, when an input level is 2 V or higher, inverter 56 regards the input level as "H" (high) and outputs an "L" (low) level, and when an input level is lower than 2 V, it regards the input level as "L" and outputs an "H" level. It is also assumed that a threshold voltage Vth of n channel MOS transistors 51-55 is 0.5 V, power supply level Vcc is 5 V, and a ground level Vss is 0 V.
When a potential of Vcc-Vth or lower is supplied to node N55, n channel MOS transistor 55 is rendered conductive, and node N55 attains ground level Vss. As a result, a super Vcc detection signal /S, which is an output of inverter 56, attains an "H" level.
When a potential higher than Vcc-Vth is supplied to node N55, this causes n channel MOS transistor 55 to have a resistance, thereby reducing the potential of node N55 to a value equal to the supplied potential minus Vcc-Vth. For example, if the potential supplied to node N55 is 6.5 V, the potential of N55 will be: 6.5-(5-0.5)=2.0 V.
As described above, this value of 2.0 V is a minimum value for inverter 56 to recognize an input of "H" level and to output an "L" level. Therefore, in order to make output /S of inverter 56 to an "L" level, a potential of 6.5 V or higher must be supplied to node N55.
The potential supplied to node N55 is equal to the potential applied to input terminal 15 minus 4.times.Vth. Accordingly, when a potential of 8.5 V (6.5 V+4.times.0.5 V=8.5 V) is applied to input terminal 15, the output of inverter 56, that is, super Vcc detection signal /S, attains an "L" level, thereby selecting the special operating mode described above.
In a normal operating mode, input terminal 15 receives an output enable signal /OE having two levels of MAX6.5 V and 0 V.
In the conventional super Vcc detection circuit 50, however, when signal /OE is applied to input terminal 15 in a normal operation, a leakage current flows from input terminal 15 through n channel MOS transistors 51-55 to ground terminal 17, resulting in a waste of current.